With continuous development of semiconductor technology, progress has been made on many aspects. For example, high-k dielectric layer has been introduced, while stress engineering technology, pocket ion implantation, as well as materials and device structures have also been steadily optimized. As a result, the size of semiconductor devices becomes smaller and smaller. However, when the feature size (or critical dimension, CD) of devices further decreases, traditional planar transistors face great challenges because short channel effect may become more prominent, fabrication process may vary, and reliability may be decreased.
As compared to planar transistors, fin type field effect transistors (fin-FETs) have fully depleted fins, lower fluctuations in the concentration of doped ions, higher carrier mobility, lower parasitic capacitances, and higher area using efficiency. Therefore, fin-FETs have attracted much attention.
During a fabrication process for integrated circuits (ICs), a plurality of metallic layers may be required to connect semiconductor devices together to form electric circuit after the formation of semiconductor device structures on a substrate. The metallic layers may include interconnecting wires and metal plugs formed in contact holes. Specifically, each metal plug formed in a corresponding contact hole may be used to connect semiconductor devices, while interconnecting wires may be used to connect the metal plugs, connecting to different semiconductor devices, together to form electric circuits. The contact holes formed in transistors include contact holes on surfaces of gate electrodes and contact holes connecting to active regions. As process nodes in ICs continue to shrink, the distance between neighboring gate electrodes also gradually decreases. Contact holes on surfaces of active regions between neighboring gate electrodes may not be able to be directly formed by a photolithography and etching process. Instead, a self-alignment process is usually adopted to form such contact holes to connect to the active regions.
However, the size of contact holes in semiconductor structures formed by an existing self-alignment method may deviate from the designed value. The connection performance of the formed metal plugs may be affected and the performance of the formed semiconductor structure may also be affected.
The disclosed fabrication method and semiconductor structure are directed to solve one or more problems set forth above and other problems in the art.